Circuit simulator is a tool that helps engineers saving resources such as time, material, and money, during the circuit development. It also helps to understand circuits better. There is a number of circuit simulators available on the market, some are free to use and yet other cost several 100k€ for a yearly use. A difference between them can be a matter of discussion, but not now. At the beginning, you will probably discover the greatest difference between the simulators based on their "look". Although circuit simulators are being developed for a longer period of time as PCs are around, they still look quite boring. Here is one example:
Oh no, it is a command-line tool. No schematic editor either.
Do not worry, you will get used to it. This is SpiceOpus, a SPICE (Simulation Program with Integrated Circuit Emphasis) based circuit simulator. Basically, SPICE it is an equation solver, that relies on electronic component models and circuit description, which we call a netlist.
For installing the SpiceOpus, please follow these instructions (Windows, Linux, MacOS (Intel, M1)).
After sucessfull installation, I invite you to create a folder with name lab_00 on your PC. Inside it, create an empty text file ex_00.cir. Let us write:
* My first circuit description
* This is a simple resistor with a voltage source.
v1 (1 0) dc=5
r1 (1 0) r=2k
.end
Let us have a look. The very first line is a name of a circuit. This line never gets interpreted, so you can also write it without the comment starting symbol *. Comments can only exist as a standalone line.
The netlist describes a simple circuit, consisting of only a voltage source v1, which we connected to nodes 1 and 0, and a resistor r1, which is connected in parallel to the voltage source v1, e.g., 1 and 0. Note that the first character of the device name encodes the device type, e.g., v in v1 stands for voltage source and r in r1 stands for resistor. The type-encoding character must be followed by a number or more characters that encode the instance. Note that v1 offers DC voltage of 5 V, and r1 has 2 kΩ resistance.
You probably wonder, where did the 1 and 0 come from. Those are node names, that we just made-up. Well, half-true! The nodename 1 was made up (it could easily be 2 or node1 or somenode), but the global ground node is always named 0. If no 0 (GND) exists in your circuit, simulator will complain with most weird error messages you can imagine.
Note that every netlist file has to end with .end.
Let us simulate this simple circuitry. Let us open the SpiceOpus and find out in which directory the program points at (works at). Type cd to the command line, and press enter. The working directory will be returned.
SpiceOpus (c) 1 -> cd
current directory: /home/vaje
SpiceOpus (c) 2 ->
Your ex_00.cir probably resides in another folder. Copy your file location from the file browser and paste it to SpiceOpus command-line, followed after cd again:
SpiceOpus (c) 1 -> cd /media/sf_vbox_share_fold/CAO/CAO202223/LAB/lab_00
current directory: /home/vaje
SpiceOpus (c) 2 ->
In Windows, your path will look something like:
SpiceOpus (c) 1 -> cd "C:/Documents and Settings/All Users/Documents/CAO/CAO202223/LAB/lab_00"
Remember to change backslashes \ to normal slash / and add double dictation marks "" when the path includes empty spaces.
Now load your ex_00.cir file into the simulator:
SpiceOpus (c) 2 -> source ex_00.cir
SpiceOpus (c) 3 ->
No output means good output (means - no errors!). Now we can run our first circuit analysis, the "Operating Point" analysis, or shortly op:
SpiceOpus (c) 2 -> source ex_00.cir
SpiceOpus (c) 3 -> op
If any error messages were thrown, read them carefully and apply corrections. But normally, when no errors, you get no output. No output is good output. Now we can observe results. Let us type:
SpiceOpus (c) 3 -> print v(1)
This will tell you voltage between the nodes 1 and the ground.
SpiceOpus (c) 6 -> print v(1)
v(1) = 5.000000e+00
Interested in the current over the r1?
SpiceOpus (c) 12 -> print i(v1)
i(v1) = -2.50000e-03
SpiceOpus (c) 13 ->
Let us note that only current over a voltage source can be printed. When interested in some other branch current, you need to place a "dummy" voltage source (DC=0) and print current over it. There is a command that lists all available nodes and branch currents in your analysis:
SpiceOpus (c) 13 -> display
To be continued.
Pasting a file, created in our first session.
Basic circuit
* commentary for some stuff to remember ...
* power supply *
v1 (1 0) dc=5 ac=1
****************
r1 (1 2) r=2k
r2 (2 0) r=1k
****************
c1 (2 0) c=50n
.control
* Starting the control block...
* Analysis commands are to be put here:
* Operating point Analysis
echo "**********************"
op
echo "Node voltages on 1 and 2:"
print v(1) v(2)
echo "Current over voltage source v1:"
print i(v1)
* DC analysis
* Parameter sweep analysis
echo "Sweeping r2..."
* at "r2"... sweep the parameter "r" from ... 1mOhm to 10kOhm with the step of 100Ohm
dc @r2[r] 1m 10k 100
*plot v(2) xlabel "r2 [Ohms]" ylabel "v(2) [V]" title "r2 parameter sweep"
echo "Sweeping v1..."
dc v1 1 10 0.1
*plot v(2) title "Sweeping a source..."
* setting a parameter to a new fixed value
let @r2[r] = 2k
op
*print v(2)
echo Transient analysis (tran...)
* create a source which is time-dependent
let @v1[pulse]= (0;5;1m;1m)
* I created a step going from 0V to 5V after 1m from start in 1m (risetime)
*tran 0.0001 0.01
* tran (step) (stop)
*plot v(2)
* _at_vin1_change_property:
* / _property
* | | _start_voltage
* | | / _stop_voltage
* | | / / _time_delay
* | | / / / _time_to_stop_voltage
* | | / / / /
let @v1[pulse]=(0;5;1m;100u;100u;1m)
* Additional possible parameters for pulse generator (in this order):
* _time_to_first_voltage (falling time)
* / _pulsewidth (time between end of rise and start to fall)
* / / _period (repeat time)
*tran 1u 3m
*plot v(1) v(2)
***********************************
echo Frequency domain (AC) analysis
* go to your signal source and add ac=1 !
ac dec 100 10 100k
* Firstly compute the transfer function
let h=v(2)/v(1)
let hmag=db(h)
let hphase=ph(h)
plot hmag
plot hphase
.endc
.end